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Add unit tests for different types of possible flip-flops importable as BLIF #414

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@mdko

#413 made the BLIF importer a little more robust by explicitly handling more flip-flops that Yosys might generate into the BLIF given our current Yosys script. We need to either create Verilog or BLIF files that exercise the new control paths in extract_flop() that are possible given those changes.

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