Right now the options for generated in reset in the output_to_verilog function is True, False, and "asynchronous". The problem is that right now the only reset that is generated is active high but most resets are actually active low. I think it is pretty easy to support the full set of options for reset at verilog generation: {none, sync active_low, sync active_high, async active_low, async active_high} and I would suggest that we do.
I don't feel strongly about maintaining backwards compatibility on this given I think the current options are kind of a hack anyways. It would be nice to make this more clear just so nobody thinks they are getting one type but are actually getting the other.
(side note, maybe this is a different request, but it would be nice for simulation to support a "reset" action that would do what the verilog output would do on reset. I think this is pretty easy to handle, but it could be more interesting if you are able to exclude some registers from the reset path but then you start worrying about x-prop!)
Right now the options for generated in reset in the output_to_verilog function is True, False, and "asynchronous". The problem is that right now the only reset that is generated is active high but most resets are actually active low. I think it is pretty easy to support the full set of options for reset at verilog generation: {none, sync active_low, sync active_high, async active_low, async active_high} and I would suggest that we do.
I don't feel strongly about maintaining backwards compatibility on this given I think the current options are kind of a hack anyways. It would be nice to make this more clear just so nobody thinks they are getting one type but are actually getting the other.
(side note, maybe this is a different request, but it would be nice for simulation to support a "reset" action that would do what the verilog output would do on reset. I think this is pretty easy to handle, but it could be more interesting if you are able to exclude some registers from the reset path but then you start worrying about x-prop!)