Faster MUL/DIV, singed and unsigned, combo's using only 1 data register for the operation instead of 2 registers + cycle gain table included.

[ManuelAndre123]

A stack "pop" to data register can be omitted speeding up the code.
Affected: MULU, MULS, DIVU, DIVS only signed examples are given but same applies for unsigned ops.

Long Multiplication (expr.c)

68020+:
          move.l  (sp)+,d1
          move.l  (sp)+,d0
          muls.l  d1,d0
          move.l  d0,-(sp)
       
Long Division (expr.c)
        ~~~~~~~~~~~~~~~~~~~~~~
68020+:
          move.l  (sp)+,d1
          move.l  (sp)+,d0
          divs.l  d1,d0
          move.l  d0,-(sp)
       
Versus MY CODE:       ; lines can be discarded

Long Multiplication (expr.c)
        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
68020+:
          move.l  (sp)+,d1
        ;  move.l  (sp)+,d0
          muls.l  (sp)+,d1
          move.l  d1,-(sp)
       
Long Division (expr.c)
~~~~~~~~~~~~~~~~~~~~~~
68020+:
          move.l  (sp)+,d0
        ;  move.l  (sp)+,d0
          divs.l  (sp)+,d0
          move.l  d0,-(sp)

Gain is: (look at MY CODE:). Small gain but most have a 68030 or emulated by qemu (not sure what type of cpu qemu emulates)
       
        68020 ~2 cycles saved
        68030 ~2 cycles saved
        68040 ~1 cycle  saved
        68060 0–1 cycle saved