I created a few lessons in my own fork of this repo, for Verilog which would be useful for easing people into Sys-Verilog. Feel free to grab some lessons. Bear in mind I am still in the process of learning so there may be some mistakes here and there. https://github.com/samir-shah-ahmed/chip-design-tutorial.git.
I created a few lessons in my own fork of this repo, for Verilog which would be useful for easing people into Sys-Verilog. Feel free to grab some lessons. Bear in mind I am still in the process of learning so there may be some mistakes here and there. https://github.com/samir-shah-ahmed/chip-design-tutorial.git.