riscv: add generic way to detect if inside interrupt context

[bbawj]

Description

There is currently no extension agnostic way to detect interrupt nesting in RISC-V. The RP2350 port contains a custom meicontext CSR register. There is also alternatively the CLIC extension which would expose the mintstatus CSR.

In the absence of those, this patch adds xInterruptNesting as a global variable. The old value is stored on the stack context before being incremented when executing the portSAVE_CONTEXT_INTERNAL macro. The old value is restored in the portRESTORE_CONTEXT macro

Test Steps

Compiled using riscv32-unknown-elf-gcc and ran kernel demos in qemu-system-riscv32 virt machine.

Checklist:

• I have tested my changes. No regression in existing tests.
• I have modified and/or added unit-tests to cover the code changes in this Pull Request.

Related Issue

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[sonarqubecloud]

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud