Systems Engineer | Low-Level Architecture & Kernel

Bridging the gap between bare-metal execution, hardware architecture, and resilient infrastructure. I combine algorithmic rigor (SBC/ICPC) with kernel-level engineering, custom Linux builds, and RISC-V ISA research to build systems with zero-overhead abstractions.

Systems, Kernel & Low-Level

Infrastructure, SRE & Observability

Learning

• RISC-V & Embedded Linux (Ternary Edge): Building virtualized Linux distributions via Buildroot for NPU architectures on FPGA. Currently researching RISC-V ISA extensions with a focus on Control-Flow Integrity (CFI) and Data-Flow Integrity (DFI) implementations.
• Kernel & SRE Dynamics: Stress-testing compute-heavy algorithms (2-SAT, N-Queens) under strict cgroups v2 isolation. Analyzing page faults, cache lines, and memory pressure to simulate low-level bottleneck dynamics and failure modes.
• Algorithmic Optimization: SBC/ICPC competitive programming background. Deep focus on memory alignment, custom allocators, graph theory, and execution under strict time/space complexity limits in C/C++ and Rust.
• Homelab & Bare-Metal Networking: Designing on-premise infrastructure using repurposed hardware to analyze raw TCP/IP stack performance, custom DNS routing, and physical resource constraints.

• Focus Areas: RISC-V architecture, Linux Kernel toolchains, low-level security mitigations (CFI/DFI), and eBPF-based observability.
• Current Objective: Applying systems programming expertise to CNCF and RISC-V International open-source projects, bridging the gap between compiler output, ISA execution, and kernel security.