Resolve syncing conflicts from FromPrivateLiveToMaster to main

.github/workflows/generate-preview-links.yml

@@ -0,0 +1,25 @@
+name: 'Preview link generator'
+
+on:
+  pull_request_target:
+    types: [opened, synchronize, reopened]
+
+permissions:
+  contents: read
+
+jobs:
+  preview_link_generator_job:
+    name: Generate preview link table
+    runs-on: ubuntu-latest
+    permissions:
+      statuses: read
+      pull-requests: write
+    steps:
+      - name: Harden Runner
+        uses: step-security/harden-runner@b09bb98e06d4d774595224525879c09bc6e98c40 # v2.20.1
+        with:
+          egress-policy: audit
+
+      - uses: dotnet/docs-tools/actions/preview-link-generator@main
+        with:
+          repo_token: ${{ secrets.GITHUB_TOKEN }}

docs/build/reference/arch-x64.md

@@ -7,7 +7,7 @@ helpviewer_keywords: ["/arch:SSE2 compiler option [C++]", "/arch:SSE4.2 compiler
 ---
 # `/arch` (x64)
 
-Specifies the architecture for code generation on x64. These switches apply to the x64 targeting version of the compiler. For more information on **`/arch`** for other target architectures, see [`/arch` (x86)](arch-x86.md), [`/arch` (ARM64)](arch-arm64.md), and [`/arch` (ARM)](arch-arm.md).
+Specifies the architecture for code generation on x64. These switches apply to version of the compiler that targets x64. For more information about **`/arch`** for other target architectures, see [`/arch` (x86)](arch-x86.md), [`/arch` (ARM64)](arch-arm64.md), and [`/arch` (ARM)](arch-arm.md).
 
 ## Syntax
 
@@ -16,25 +16,25 @@ Specifies the architecture for code generation on x64. These switches apply to t
 ## Arguments
 
 **`/arch:SSE2`**\
-Enables Intel Streaming SIMD Extensions 2. The default instruction set is SSE2 if no **`/arch`** option is specified.
+Enables x64 Streaming SIMD Extensions 2. If you don't specify a **`/arch`** option, the default instruction set is SSE2.
 
 **`/arch:SSE4.2`**\
-Enables Intel Streaming SIMD Extensions 4.2.
+Enables x64 Streaming SIMD Extensions 4.2.
 
 **`/arch:AVX`**\
-Enables Intel Advanced Vector Extensions.
+Enables x64 Advanced Vector Extensions.
 
 **`/arch:AVX2`**\
-Enables Intel Advanced Vector Extensions 2.
+Enables x64 Advanced Vector Extensions 2.
 
 **`/arch:AVX512`**\
-Enables Intel Advanced Vector Extensions 512.
+Enables x64 Advanced Vector Extensions 512.
 
 **`/arch:AVX10.1`**\
-Enables Intel Advanced Vector Extensions 10 version 1.
+Enables x64 Advanced Vector Extensions 10 version 1.
 
 **`/arch:AVX10.2`**\
-Enables Intel Advanced Vector Extensions 10 version 2.
+Enables x64 Advanced Vector Extensions 10 version 2.
 
 ## Remarks
 

docs/build/reference/arch-x86.md

@@ -7,7 +7,7 @@ helpviewer_keywords: ["/arch:IA32 compiler option [C++]", "/arch:SSE compiler op
 ---
 # `/arch` (x86)
 
-Specifies the architecture for code generation on x86. These switches apply to the x86 (32-bit) targeting version of the compiler. For more information on **`/arch`** for other target architectures, see [`/arch` (ARM64)](arch-arm64.md), [`/arch` (x64)](arch-x64.md), and [`/arch` (ARM)](arch-arm.md).
+Specifies the architecture for code generation on x86. These switches apply to the version of the compiler that targets x86 (32-bit). For more information about **`/arch`** for other target architectures, see [`/arch` (ARM64)](arch-arm64.md), [`/arch` (x64)](arch-x64.md), and [`/arch` (ARM)](arch-arm.md).
 
 ## Syntax
 
@@ -19,25 +19,25 @@ Specifies the architecture for code generation on x86. These switches apply to t
 Specifies no enhanced instructions and also specifies x87 for floating-point calculations.
 
 **`/arch:SSE`**\
-Enables Intel Streaming SIMD Extensions.
+Enables Streaming SIMD Extensions.
 
 **`/arch:SSE2`**\
-Enables Intel Streaming SIMD Extensions 2. The default instruction set is SSE2 if no **`/arch`** option is specified.
+Enables Streaming SIMD Extensions 2. If you don't specify an **`/arch`** option, the default instruction set is SSE2.
 
 **`/arch:AVX`**\
-Enables Intel Advanced Vector Extensions.
+Enables Advanced Vector Extensions.
 
 **`/arch:AVX2`**\
-Enables Intel Advanced Vector Extensions 2.
+Enables Advanced Vector Extensions 2.
 
 **`/arch:AVX512`**\
-Enables Intel Advanced Vector Extensions 512.
+Enables Advanced Vector Extensions 512.
 
 **`/arch:AVX10.1`**\
-Enables Intel Advanced Vector Extensions 10 version 1.
+Enables Advanced Vector Extensions 10 version 1.
 
 **`/arch:AVX10.2`**\
-Enables Intel Advanced Vector Extensions 10 version 2.
+Enables Advanced Vector Extensions 10 version 2.
 
 ## Remarks
 

docs/build/reference/feature-arm64.md

@@ -16,6 +16,8 @@ To enable one or more features the targeted ARM64 extension supports, specify on
 
 | Feature argument | Feature identifier | Optional from | Enabled by default | Description | Supported in version
 |--|--|--|--|--|--|
+|**`cssc`**  | `FEAT_CSSC` | Armv8.7 | Armv8.9 | Common Short Sequence Compression instructions. | Visual Studio 2026 18.10 (MSVC 14.52)
+|**`faminmax`**  | `FEAT_FAMINMAX` | Armv9.2 | Armv9.5 | Floating-point maximum and minimum absolute value instructions. | Visual Studio 2026 18.10 (MSVC 14.52)
 |**`lse`**   | `FEAT_LSE` | Armv8.0  | Armv8.1 | Large System Extensions. | Visual Studio 2022 17.10
 |**`rcpc`**  | `FEAT_LRCPC` | Armv8.2 | Armv8.3 | Load-Acquire RCpc instructions. | Visual Studio 2022 17.10
 |**`rcpc2`**  | `FEAT_LRCPC2` | Armv8.2 | Armv8.4 | Load-Acquire RCpc instructions v2. | Visual Studio 2022 17.11