I like building things from the gates up. Over the last couple of years that's meant a 16-bit CPU made of elementary logic gates, a self-reconfiguring FPGA SoC, and a small x86 kernel — and, just as often, the testbenches and CI that prove they actually work.

Most of my projects live at the seam between hardware and software: RTL and verification on one side, C and low-level systems on the other. I'm especially drawn to processor and FPGA design, and to the idea of eventually working on GPUs, AI accelerators, and consumer silicon.

• protean — A self-reconfiguring FPGA handheld: a picorv32-based SoC on a Tang Nano 20K that hot-swaps between runtime personas (a Game Boy, a logic analyzer). Hand-written RTL for I²C, SPI-flash, and video timing, clock-domain crossing on a dual-clock framebuffer, self-checking testbenches, and a fully open-source toolchain (Yosys · nextpnr · Apicula).

• Hack-16-CPU-Verilog — A working 16-bit computer (Hack ISA) built from elementary logic gates up through the ALU, CPU, and RAM in Verilog — plus a custom assembler that turns symbolic assembly into machine code the processor runs.

• nue-kernel — A homebrew i386 x86 kernel in C and assembly: bootloader handoff, GDT/IDT, and a physical memory manager, brought up and debugged in QEMU + GDB.

• RISC-V (U of T Open Source Society) — Contributing SystemVerilog RTL and testbenches to a 5-stage RV32I pipeline targeting FPGA synthesis.

• ViSTA — Vibro-Sensory Travel Aid — An award-winning navigation headset for the blind (< $100, 54 ms latency) using computer vision offloaded to mobile, tested with the CNIB. Rick Hansen Difference Maker of the Year, 2025.

Languages

Hardware & EDA

Platforms

• Building — protean, and the verification tooling around my hardware projects
• Learning — SystemVerilog verification (UVM, functional coverage, assertions) and timing closure
• Seeking — Summer 2027 internships in Design Verification / RTL / low-level systems
• Ask me about — FPGAs, CPU design, kernels, and retro-hardware restomods