FPGA developer and Electronics Hardware Designer based in Stockholm / Sweden
Email / LinkedIn
I am an enthusiastic designer with a keen interest in mathematics, electronics circuits, FPGA architecture, and signal processing. With a master’s degree in electronics engineering, specializing in circuits and systems, I have contributed to academic research and industrial design projects across several countries, including Taiwan and Hong Kong, before relocating to Sweden. During my time as an FPGA developer, I worked with a variety of families, including Altera, Xilinx's Spartan 3, Spartan 6, Artix-7, and Zynq series.
I created numerous AXI-based communication modules and test benches for FPGAs. In addition, I've created testbenches using open-source frameworks such as OSVVM, VUnit, and the UVVM framework, which include reusable verification components (VCs), bus functional models (BFMs), and advanced logging/assertions for FPGA RTL verification and image processing with FPGAs. VHDL was used to implement and verify a simple RISC-V RV32I core. I also created Wishbone-compatible RTL modules and TBs for point-to-point and shared bus topologies. Python RTL models were created in cocotb, interfacing VHDL/Verilog DUTs for reference checks and self-testing. Implemented and verified a custom 256-point fixed-point FFT (radix-2 DIT) in VHDL, including state-machine control, twiddle generation, and comprehensive testbench validation.
In addition to hardware development, I created numerous high-speed communication data acquisition I/O boards based on the Xilinx and Altera FPGA families. This required a schematic design and layout of a multi-layer PCB to ensure optimal power and signal integrity. To fine-tune the platform for peak performance, I performed testing, debugging, and hardware-in-the-loop verification.
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FPGA, CoS & ASIC devices
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VLSI & low-power design
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Real-Time system & software Co-Design
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Digital signal & image processing
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High-speed circuits and PCB design
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Bio-electronics & Bioinstrumentation circuits and systems
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Hardware-in-the-Loop test & verification
- Erfan Abbasian, Shilpi Birla, and Emad Mojaveri, Design and Investigation of Stability- and Power-Improved 11T SRAM Cell for Low-Power Devices International Journal of Circuit Theory and Applications (IJCTA), 2022
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Electronics Hardware Designer & FPGA developer @ HitachiEnergy, Stockholm / Sweden (May 2022 - Peresent)
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FPGA Design & Electronics Hardware Research Assistant @ City University of Hong Kong, Hong Kong SAR (Oct. 2020 to Mar. 2022)
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Electronics System Researcher @ National Chiao Tung University, Hsinchu City / Taiwan (Jan. 2020 to Sep. 2020)
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Electronics System Research Assistant @ Smart Control Developing Technology Co. (Imam Khomeini International University - IKIU), Qazvin Province / Iran (Jun. 2018 to Sep. 2019)
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Electronics Hardware & System Designer @ Subar Science & Technology Co. (MatsaJet), Guilan Province / Iran (Apr. 2016 to Feb. 2018)
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Electrical Expert @ Antique Co., Guilan Province, Iran (Apr. 2014 to Jan. 2016)
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Automation & Instrumentation Technical Expert @ Khazar Steel Complex, Guilan Province / Iran (Sep. 2013 to Feb. 2014)
- M.Sc. Electrical Engineering - Electronics, Azad University, Science and Research Branch, Tehran / Iran - GPA: 3.3 (16.5 / 20)
- B.Sc. Electrical Engineering - Electronics, University of Guilan, Rasht / Iran - GPA: 3.53 (17.69 / 20)
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English (Fluent)
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Swedish (Basic Level)
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Persian (native speaker)
