GitHub - ironsdan/mips_processor: A simple, 5 stage pipelined, MIPS style processor written in Verilog. · GitHub

This repository was archived by the owner on Aug 5, 2024. It is now read-only.

Name		Name	Last commit message	Last commit date
FPU		FPU
2To1Mux.v		2To1Mux.v
3To1Mux.v		3To1Mux.v
ALU.v		ALU.v
Controller.v		Controller.v
DataMemory.v		DataMemory.v
ForwardingUnit.v		ForwardingUnit.v
HazardDetectionUnit.v		HazardDetectionUnit.v
InstructionMemory.v		InstructionMemory.v
PC.v		PC.v
Processor.v		Processor.v
Processor_tb.v		Processor_tb.v
RegisterFile.v		RegisterFile.v
SignExtender.v		SignExtender.v
processor_design		processor_design

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A simple, 5 stage pipelined, MIPS style processor written in Verilog.

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