LATX, feat: cross-domain FCSR flag synchronization - #469
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The current translator leaks native FCSR flags across domains when a TB mixes x87 and SSE/AVX instructions, corrupting guest exception state. Introduce a state machine (env->fcsr_flags_state) that tracks which domain (x87/SSE) owns the native FCSR sticky flags and whether they are dirty. On domain transitions, prepare_fcsr_for_domain() merges pending flags back into the previous domain's shadow register, then clears native flags and loads the new domain's rounding mode. Refactor update_sw_by_fcsr() into domain-specific helpers for flag merging, x87 status / MXCSR preparation, and TOP refresh. Signed-off-by: Zewei Yang <yangzewei@loongson.cn>
…ators In x87 arithmetic translators (FADD/FSUB/FMUL/FDIV/FSQRT and their pop/integer variants), call prepare_fcsr_for_domain() before the native FP operation; reorder operand loading so the domain switch precedes the actual computation. Remove the legacy per-instruction FCSR cause-bit checks in the FDIV family (~120 lines), now covered by the unified synchronization mechanism. Apply the same domain preparation to SSE/AVX arithmetic (ADD/SUB/MUL/DIV/SQRT), horizontal operations (HADD/HSUB/ADDSUB), dot products (DPPS/DPPD), FMA variants, and CVT/CVTT conversion translators. On save paths (FXSAVE/XSAVE), flush pending flags before the helper call. On restore paths (FXRSTOR/XRSTOR/FRSTOR), reset the domain state after loading guest register contents. Signed-off-by: Zewei Yang <yangzewei@loongson.cn>
Add four suites of freestanding x86_64 guest binaries driven by host shell scripts that compare stdout binary reports: - Flag isolation (64 cases): verify that x87 and SSE exception flags do not leak across domains, covering all arithmetic/divide/sqrt instructions and FXSAVE/XSAVE/FNCLEX/FNINIT paths. - Rounding-mode correctness (55 cases): verify that after a domain switch the rounding mode is restored from the correct shadow register, covering FLDCW/FLDENV/FRSTOR/XRSTOR and the full AVX arithmetic/FMA/horizontal/dot-product family. - CVT/CVTT exceptions (6 cases): verify that scalar and packed conversions set the expected MXCSR exception bits. - x87 pop semantics (6 cases): verify that FADDP/FMULP/FSUBP/FDIVP and their reverse variants produce the correct result and pop the x87 stack exactly once. XSAVE/XSAVEOPT and AVX cases activate automatically when the build enables the corresponding options. Registered through the existing LoongArch LAT integration test framework. Signed-off-by: Zewei Yang <yangzewei@loongson.cn>
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Background
When running the official test suites of Python scientific computing
libraries (NumPy/SciPy) under LAT, some floating-point exception
detection tests failed. The root cause is native FCSR flags leaking
between the x87 and SSE domains.
x86 exposes two independent sets of floating-point exception state:
However, LoongArch native floating-point operations share a single
FCSR. Allowing x87 and SSE/AVX instructions to use the same native
FCSR directly causes:
incorrectly observed in the other domain's shadow state
Solution
Introduce an owner/dirty state for native FCSR flags:
domain and not yet committed to the guest shadow
shadow register
Each TB maintains a local domain cache to skip redundant preparation
for consecutive instructions in the same domain. When reading or
saving architectural state, only the dirty owner's native flags are
committed, preventing cross-contamination between x87 and SSE.
Patch structure
1/3 Introduce state machine and cross-domain synchronization infra
2/3 Wire synchronization into floating-point translators
3/3 Add integration tests (131 cases)