Fix mx.from_fp8 E4M3FN NaN decode with branchless carry - #4376
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## The Bug - Byte 0x7f decodes to 480.0 instead of +NaN - Byte 0xff decodes to -480.0 instead of -NaN ## The Fix Changed decode from: v = (x & 127) << 7; // Wrong: gives ±480.0 To: v = x & 127; u = (v << 7) | (((v + 1) >> 7) << 14); // Right: gives ±NaN How it works: - 0x7f → v = 0x7f → arithmetic sets NaN bit → +NaN - 0xff → v = 0x7f → arithmetic sets NaN bit → then sign bit negates it → -NaN Same 7 bits, sign handled by existing path. No branches, just arithmetic.
Collaborator
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Some tests are failing, do you mind take a look? |
…stead of actually checking anything.
Author
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Set the NaN correctly but then negated it to flip the sign, which doesn't work. Now I will embed the sign bit directly in the fp16 encoding instead. |
Author
I will dig a bit deeper into this and add a fix. |
…e code sets that sign correctly, but the × 256 step swaps the whole NaN for the hardware's canonical one, and IEEE 754 doesn't require otherwise.
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Fixes #4135
The Bug
The Fix
Changed decode from:
v = (x & 127) << 7; // Wrong: gives ±480.0
To:
v = x & 127; u = (v << 7) | (((v + 1) >> 7) << 14); // Right: gives ±NaN
How it works:
Same 7 bits, sign handled by existing path. No branches, just arithmetic.