#

de0

Here are 5 public repositories matching this topic...

Furinaaa-Cancan / DE0-FPGA-Labs

DE0 FPGA Labs (Terasic DE0, Cyclone III EP3C16F484C6) — collection of practical projects: arbitrary waveform generator (stage 2-3), ultrasonic RF echo envelope extraction with 7 methods + 3-peak detection + Qt GUI (stage 4).

fpga verilog dds quartus awg de0 cyclone-iii

Updated May 28, 2026
Python

arnaldojr / Robot-FPGA

Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.

fpga robo altera vhd l298n l298 altera-fpga l298n-h-bridge engenharia-de-computacao insper de0 de0cv de0-cv robot-fpga robo-fpga

Updated Nov 1, 2019
VHDL

HTL-inn / vhdl-template

Template for VHDL projects (using the DE0 board)

vhdl de0-board de0

Updated Mar 9, 2020
VHDL

eliherm / Scrolling-Marquee

Scrolling marquee for the Altera DE0 board

embedded-systems nios-ii de0 scrolling-marquee

Updated Jan 27, 2020
C

AlexLevitin / VHDL_Encryptor_Decryptor

Encryption/Decryption unit in FPGA written in VHDL with use of test benches and simulations

fpga simulation vhdl altera modelsim testbench quartus de0

Updated Sep 28, 2023

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