Water Level Meter
This repository offers a comprehensive journey through RTL digital design, ranging from fundamental concepts to advanced applications. It features Verilog code and test benches for a variety of circuits, including multiplexers,APB Systems,Simple ALU, and more complex designs such as round-robin arbiters and FIR filters.
The design, development, and implementation of a complex digital voting system built entirely from Transistor-Transistor Logic (TTL) integrated circuits.
BitCalculator is used for bitwise arithematic operations like addition, subtraction, multiplication etc.
VHDL code and testbenches for the elementary gates, memory and ALU of the NAND2TETRIS course. This was a learning experience and was my first time programming in VHDL.
Tetris is a digital puzzle game that involves stacking blocks. The player’s goal is to strategically guide and align the falling blocks to complete rows within a limited time. This game was developed as part of a digital logic course project in the Computer Engineering department at Guilan University, where we implemented it using Proteus.
Client-side Karnaugh map minimizer (2–4 variables) using Quine-McCluskey. Outputs both minimized SOP and POS expressions with color-coded implicant groups.
Lab reports for CSE231L – Digital Logic Design Lab (Summer 2024), completed under the instruction of Dr. Khaleda Ali (KdA1) at North South University.
ECE 350
A digital logic simulator for simulating digital logic circuits. Providing a drag and drop frontend, uses topological sorting for state updates and function
Utilised System Verilog to create the 74LS93 Counter
Digital Logic Design Implementation A fully hardware-based implementation of the classic Tic-Tac-Toe game using D flip-flops, logic gates, bi-color LEDs, and push-buttons alon with win of three counter and display. No microcontroller or software pure digital logic. Designed and simulated in Proteus Design Suite
Final project of the Digital Logic Design (Reti Logiche) BEng course at PoliMi
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