xillinx

🧛🏻‍♂️ Dark theme for Vivado

A real time Microprocessor impemented in verilog and tested on Xilinx Artix FPGA.

XVC 1.0 daemon j-link support for Vivado

Verilog code practice using the Xilinx Vivado design suite

FPGA Lab for Digital System Design - BS in Electronic Systems - IIT Madras

Verilog HDL based digital design projects including Vending Machine Controller, 16-bit RISC Processor, Sequence Detector and 4-bit Counter implemented and simulated using Xilinx Vivado.

Xillinx AXI Verification IP :axi_vip1.1@Vivado 2017.4

Verilog project for implementing matrix multiplication on spartan 6 nexys 3 FPGA.