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  • Shandong University
  • Jinan
  • 13:55 (UTC +08:00)

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vilesmeier/README.md

一只沙发上的大懒猫

About Me

B.Eng. in Electrical Engineering @ Shandong University

M.Eng. in Electrical Engineering @ Shanghai Jiaotong University

NUEDC 2024–2025 participant · 24B / 25A

  • 25A National First Prize · Team Leader
  • Full-stack experience in power electronics software, hardware, simulation, and debugging

Technical Skills

Category Technologies
MCU / FPGA C2000 · FPGA · Zynq
Programming C · Verilog
Development Code Composer Studio (CCS) · Vivado · Vitis · Quartus
Hardware Design LCEDA · Altium Designer
Simulation MATLAB/Simulink · PSIM · PLECS · Multisim

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  1. vilesmeier vilesmeier Public

    GitHub Profile README