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Fix M-extension funct7 decoding - #358

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tinebp merged 2 commits into
vortexgpgpu:masterfrom
cassuto:fix_m_extension_funct7_decode
Aug 29, 2026
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Fix M-extension funct7 decoding#358
tinebp merged 2 commits into
vortexgpgpu:masterfrom
cassuto:fix_m_extension_funct7_decode

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@cassuto

@cassuto cassuto commented Jun 3, 2026

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Previously it used (funct7 & 0x1), which could decode reserved odd funct7 values as M-extension instructions while RTL requires the exact 7'b0000001 encoding. This masked illegal instructions instead of triggering abort().

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tinebp commented Aug 29, 2026

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Verified on master @ 1c3403d: the bug is live at sim/simx/decode.cpp:524funct7 & 0x1 decodes reserved odd funct7 values (0x3, 0x5, 0x21, …) as M-extension ops, while the RTL decoder's exact case (funct7) match falls through to the base-ALU default for them. That is a functional SimX↔RTL divergence: e.g. an R-type word with funct7=0x3, funct3=0 executes as MUL on SimX and as ADD on RTL. Applied the fix locally: all 8 rv32um-p-* ISA tests pass, plus the full tests/regression simx suite (81/81).

Why CI never caught it: no compiler emits reserved encodings, and no test in the tree exercises them — CI only ever sees canonical funct7 values. A conform test that executes a reserved-funct7 word via .insn and asserts the RTL-matching decode (base-ALU ADD, not MUL) will be added alongside this fix so the kernel CI category (simx + rtlsim, both XLENs) locks the parity in.

Code review: one-line change, matches the C++ guidelines; the other funct7 & 0x1 uses in the file (RV64 shamt bit, FPU fmt) are legitimate and correctly untouched.

Note on merging: this branch carries the pre-3.0 history (no common ancestor with today's master), so it will be squash-merged to keep master's history clean — your authorship is preserved in the squashed commit.

Accepting.

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Verified locally: rv32um ISA suite + full simx regression pass; decode now matches the RTL's exact funct7 case-match.

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tinebp merged commit 3eed952 into vortexgpgpu:master Aug 29, 2026
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tinebp commented Aug 29, 2026

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CI coverage for this fix landed in #398 — a conform test executing a reserved funct7 encoding and asserting the RTL-matching decode (validated to fail under the pre-fix behavior).

tinebp added a commit to RunjiaChen/vortex-visualiser that referenced this pull request Aug 30, 2026
Follow-up to vortexgpgpu#358: executes a reserved OP encoding (funct7=0x3,
funct3=0) via .insn and asserts the RTL-matching base-ALU decode (ADD).
Under the pre-vortexgpgpu#358 SimX bug this word ran as MUL (r=63 instead of 16),
so the test locks the SimX<->RTL decode parity in for CI (kernel
category, simx + rtlsim, both XLENs).

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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2 participants