vm: banked L1 TLB and a device-level shared page-table walker - #406
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…L1_TLB_NUM_BANKS) Adds VX_tlb_l1_banked behind VX_tlb_l1's parent contract: the entry array splits into power-of-two single-ported banks selected by the low VPN bits (a losing lane holds for a cycle via bank_conflict), and each bank holds one parked miss — a miss blocks only its bank while the others keep hitting; a walk in flight across a flush is discarded and re-walked. The knob defaults to 0, which elaborates the baseline multi-ported CAM + MSHR unchanged; the banked organization from vortexgpgpu#392 becomes a reachable configuration for same-base comparison (cycle A/B by config flip, and the synthesis area/timing comparison banking exists for). Kill/fault, flush, drain, and perf contracts match the baseline. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Replace the multi-ported CAM + shared-MSHR L1 TLB with the banked organization in place: VX_tlb_l1.sv now holds the banked storage + miss station (previously VX_tlb_l1_banked.sv behind a config select), and VX_mmu instantiates it unconditionally. The entry array splits into VX_CFG_L1_TLB_NUM_BANKS single-ported banks (low VPN bits select); each bank answers one lane per cycle and holds one parked miss, so a miss blocks only its bank while the others keep hitting. Trades the full multi-port CAM + shared MSHR for per-bank ports and slots: cheaper lookup hardware at scale, one outstanding walk per bank. Validated (banked, 4 banks, with the device-level walker): full vm catalog green on rtlsim-32 (23), simx-32 (21, incl. model parity) and rtlsim-64 (23); demo at 1 and 2 clusters; -Wall clean. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01DJk9ipw4g1ZP3zZShiYaMq
Lift the per-cluster VX_ptw to one shared walker at the device, the shared-walker organization from the GPU-MMU literature. Each cluster exports its L2 TLB's miss bus (new dev_ptw_if port); a VX_tlb_bus_arb folds the clusters into the walker, whose PTE fetches ride a dedicated LLC client port (per_cluster_mem_bus_if[L3_PTW_IDX]) instead of competing with the sockets inside each cluster's L2 cache — the L2 PTE-fetch client slot is removed outright (L2_PTW_REQS = 0), returning that arbitration bandwidth to the cores. The walker's flush-done leg joins the DCR done-tree through cluster 0's slot, and its structural faults land on cluster 0's fault lines (the DCR fault latch is device-global, so attribution is preserved). One walk cache now serves all clusters. Topologically identical to the per-cluster walker at NUM_CLUSTERS=1; the organizations diverge at 2+ clusters. The MMU synthesis sandbox (hw/unittest/vm) follows: walker behind the device arb, PTE fetches exiting at a dedicated top-level port at the production LLC-client boundary. Validated together with the banked L1: full vm catalog green on rtlsim-32 (23), simx-32 (21, incl. model parity) and rtlsim-64 (23); demo at 1 and 2 clusters; -Wall clean. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01DJk9ipw4g1ZP3zZShiYaMq
The banked VX_tlb_l1 had ported the old per-bank parked-miss slot, which dropped MMU v2's non-blocking miss handling (multiple outstanding walks, same-VPN dedup, hit-under-miss inside a bank). Put VX_tlb_mshr back behind the banked CAMs, wired as master wires it; the MSHR install routes to the bank of the walked VPN. MSHR_SIZE/REPLAY_DEPTH return as VX_mmu parameters and the walk id is the MSHR slot again. The L1 proposal is now only the banked entry array: single-lookup-port banks selected by low VPN bits (bank_conflict holds losing lanes) in front of an unchanged miss station. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01DJk9ipw4g1ZP3zZShiYaMq
Mirror the RTL topology in the cycle model: the Ptw moves from Cluster to ProcessorImpl behind a PtwMux that folds every cluster's L2-TLB miss link into one walker (cluster index in the high slot bits, like VX_tlb_bus_arb) and fetches PTEs on the new last LLC input (VX_CFG_L3_PTW_IDX). The cluster L2 port 0 is bound directly again; SATP fan-out, the fault latch, drain and the MPM PTW counters follow the walker to processor scope. The per-core Tlb is partitioned into VX_CFG_L1_TLB_NUM_BANKS banks by low VPN bits and the Mmu forward path grants each bank's lookup port to the lowest requesting port per tick; the MSHR path is unchanged. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01DJk9ipw4g1ZP3zZShiYaMq
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#392 but just the main PTW & TLB architecture
rebased to current master
simx is updated to remain a timing twin (walker at processor scope behind a mux, banked L1 with per-bank lookup grants), so model_parity tests reflect the real topology; the MPM PTW counters move with the walker. The hw/unittest/vm synthesis sandbox is rewired to the device topology with the walker memory port at the top. (Should I break this up further into simx and rtl?)
Validation (all on this base): vm catalog 23/23 rtlsim and 21/21 simx at XLEN 32 and 64; 1- and 2-cluster demo on rtlsim and simx; 2-cluster sgemm through the arbiter path; Verilator -Wall clean.