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Introduce an astcenc-avx512 product binary (SIMD_WIDTH=16), implement gatherf and vtable lookups with VBMI permutes, and hoist float-table loads at the hot encode sites so the same table stays register-resident.
Describe astcenc-avx512 in the README, changelog, and build guide, cover gatherf/vtable in test_simd (including VLA round tests that are multiples of SIMD_WIDTH), and accept --encoder avx512 in the Python CLI and image test runners.
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Summary
astcenc-avx512: a compile-time 16-wide AVX-512 encoder, same idea as the existing AVX2 8-wide build.vgatherdps. Needs AVX-512F and AVX-512VBMI. Other ISAs, including NEON, are unchanged.Build
cmake -DCMAKE_BUILD_TYPE=Release -DASTCENC_ISA_AVX512=ON -DASTCENC_INVARIANCE=ON ..
Testing
ctestAVX-512 unit tests (SIMD width 16,gatherf_table16/32/64/144)--encoder avx512)6×6 -mediumASTC bit-identical (76559cfd…)Performance
Speedup is main AVX2 coding time / this binary (
>1= this PR is faster). Small set, 3 repeats, encodes ≥2 ms. Invariance on.Ryzen 7 9700F — Clang 18,
-j 8Pinned 6×6 medium (
taskset -c 4,-j 1): 0.0836 s → 0.0621 s (1.35×).Ryzen 7 9700F — g++ 13.3,
-j 8Pinned 6×6 medium: 0.0796 s → 0.0635 s (1.25×).
Xeon Platinum 8380 (Ice Lake) — g++ 14.3, encode-only 20 Small PNGs,
-j 8Pinned 6×6 medium: 0.1239 s → 0.1214 s (1.02×). The 16-wide/VBMI win is a Zen 5 result; Ice Lake is flat at 6×6 and loses 12×12 (64-float table cap + 512-bit license).
Apple M5 — NEON vs main NEON, Apple Clang 17
Pinned 6×6 medium: 0.0542 s vs 0.0541 s. Same ASTC hashes as x86 (
76559cfd…/6412a7ae…). ARM is unchanged.Commits
avx512package,test_simd, Python--encoder avx512