parameterized-design

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venkatalakshmilanda / parameterized_register_file

A parameterized Verilog Register File featuring synchronous write, dual asynchronous read ports, configurable data width and memory depth, along with a comprehensive testbench for functional verification.

asic fpga verilog vlsi testbench digitaldesign rtl-design hardware-design registerfile parameterized-design

Updated Jul 23, 2026
Verilog

shreekanthkapparagaon / parameterized-apb3-slave

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Parameterized AMBA APB3 Slave Peripheral in Verilog with configurable register bank, reusable APB Master BFM, and self-checking verification environment.

asic fpga verification rtl verilog gtkwave vlsi iverilog digital-design apb rtl-design bus-protocol apb3 parameterized-design

Updated Jul 5, 2026
Verilog

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