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Fix simx jalr target alignment - #339

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cassuto wants to merge 3 commits into
vortexgpgpu:masterfrom
cassuto:fix_pc_misaligned
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Fix simx jalr target alignment#339
cassuto wants to merge 3 commits into
vortexgpgpu:masterfrom
cassuto:fix_pc_misaligned

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@cassuto

@cassuto cassuto commented Apr 24, 2026

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This fixes JALR target address alignment in sim/simx by clearing bit 0 of the computed target, as required by the RISC-V ISA.
It also adds a regression test under tests/regression/jalr.

Copilot AI review requested due to automatic review settings April 24, 2026 02:37

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Pull request overview

This PR corrects RISC-V JALR target address alignment in the sim/simx emulator by clearing bit 0 of the computed target address, and adds a focused regression test to prevent the issue from reappearing.

Changes:

  • Fix sim/simx JALR next-PC computation to enforce (rs1 + imm) & ~1.
  • Add a new tests/regression/jalr test (host + kernel + startup) that fails deterministically when JALR doesn’t clear bit 0.
  • Wire the new regression into the top-level tests/regression/Makefile targets (build/run/clean).

Reviewed changes

Copilot reviewed 7 out of 7 changed files in this pull request and generated no comments.

Show a summary per file
File Description
sim/simx/execute.cpp Masks off bit 0 when computing JALR target PC to match the ISA requirement.
tests/regression/Makefile Adds the new jalr regression to aggregate build/run/clean targets.
tests/regression/jalr/Makefile Build/run glue for the new regression test.
tests/regression/jalr/start.S Minimal startup that calls main, dumps perf, and terminates.
tests/regression/jalr/main.cpp Host-side test runner that launches the kernel and validates per-core pass signatures.
tests/regression/jalr/kernel.cpp Kernel that uses an intentionally odd JALR target to distinguish correct vs incorrect alignment behavior.
tests/regression/jalr/common.h Kernel argument struct for passing the destination buffer address.

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@tinebp

tinebp commented May 11, 2026

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this bug cannot be created via compiler unless the compiler has a bug..
this can only trigger from manual assembly code.
the provided test doesn't use CPU-GPU execution model, should be moved into tests/kernel tree
recvommend adding a new test scenario to kernel/conform/

@cassuto
cassuto force-pushed the fix_pc_misaligned branch from 1c34778 to 91e315c Compare June 2, 2026 12:17
@cassuto

cassuto commented Jun 2, 2026

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this bug cannot be created via compiler unless the compiler has a bug.. this can only trigger from manual assembly code. the provided test doesn't use CPU-GPU execution model, should be moved into tests/kernel tree recvommend adding a new test scenario to kernel/conform/

Thank you for the suggestion. We have moved the tests into tests/kernel/conform tree. fixed in 91e315c

tinebp pushed a commit that referenced this pull request Aug 29, 2026
The RISC-V ISA requires JALR to clear bit 0 of the computed target
(rs1 + imm). SimX carried the bit into the warp PC, while release RTL
builds drop it implicitly through from_fullPC() PC truncation - a
SimX<->RTL divergence reachable from hand-written assembly.

Adds a conform test that lands on an intentionally odd JALR target via
an overlapped instruction word, so fixed and unfixed builds both decode
valid instructions but produce different pass/fail signatures. Runs in
CI through the kernel category (simx + rtlsim, both XLENs).

Rebase of PR #339 (original targeted the retired sim/simx/execute.cpp).

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
@tinebp

tinebp commented Aug 29, 2026

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Review (maintainer)

Verified on master @ 1c3403d: bug still live — the JALR path moved to sim/simx/alu_unit.cpp (warp.PC = rs1_data[thread_last].i + offset;, unmasked) after execute.cpp was retired in the 3.0 refactor. Your conform test fails on unfixed SimX with the expected signature (value=0x2468ace0) and passes with the ported fix; release rtlsim passes as-is (RTL truncates bit 0 implicitly in from_fullPC()), so the fix also restores SimX↔RTL parity. Full simx regression suite: 81/81 with the fix.

Why CI missed it: only hand-written assembly can produce a misaligned JALR target; nothing in the tree exercised it. Your conform test closes that (CI kernel category runs conform on simx + rtlsim at both XLENs) — no extra CI wiring needed.

Code review: clean per docs/coding_guidelines_cpp.md; kept your test verbatim (the overlapped-instruction-word design is exactly right), switched rs1 to the unsigned accessor in the port.

Merge mechanics: this branch predates the 3.0 history rewrite (no common ancestor with master, +3600 legacy commits), so it can't be merged or updated in place. The fix and test are landing via #396 with your authorship on the commit. Accepting and closing this PR in favor of #396 — thank you for the fix and the excellent test!

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Accepted — landing via #396 (rebased, your authorship preserved).

tinebp added a commit that referenced this pull request Aug 29, 2026
simx: clear bit 0 of the JALR target address (rebase of #339)
@tinebp tinebp closed this in #396 Aug 29, 2026
@tinebp

tinebp commented Aug 29, 2026

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Credit note: this fix is landed on master as commit 0326799 ("simx: clear bit 0 of the JALR target address"), authored by @cassuto — the fix and the conform test are theirs; only the rebase onto the post-3.0 tree was done by the maintainers. Thank you for the contribution!

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3 participants