Fix simx jalr target alignment - #339
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Pull request overview
This PR corrects RISC-V JALR target address alignment in the sim/simx emulator by clearing bit 0 of the computed target address, and adds a focused regression test to prevent the issue from reappearing.
Changes:
- Fix
sim/simxJALR next-PC computation to enforce(rs1 + imm) & ~1. - Add a new
tests/regression/jalrtest (host + kernel + startup) that fails deterministically when JALR doesn’t clear bit 0. - Wire the new regression into the top-level
tests/regression/Makefiletargets (build/run/clean).
Reviewed changes
Copilot reviewed 7 out of 7 changed files in this pull request and generated no comments.
Show a summary per file
| File | Description |
|---|---|
sim/simx/execute.cpp |
Masks off bit 0 when computing JALR target PC to match the ISA requirement. |
tests/regression/Makefile |
Adds the new jalr regression to aggregate build/run/clean targets. |
tests/regression/jalr/Makefile |
Build/run glue for the new regression test. |
tests/regression/jalr/start.S |
Minimal startup that calls main, dumps perf, and terminates. |
tests/regression/jalr/main.cpp |
Host-side test runner that launches the kernel and validates per-core pass signatures. |
tests/regression/jalr/kernel.cpp |
Kernel that uses an intentionally odd JALR target to distinguish correct vs incorrect alignment behavior. |
tests/regression/jalr/common.h |
Kernel argument struct for passing the destination buffer address. |
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this bug cannot be created via compiler unless the compiler has a bug.. |
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Thank you for the suggestion. We have moved the tests into tests/kernel/conform tree. fixed in 91e315c |
The RISC-V ISA requires JALR to clear bit 0 of the computed target (rs1 + imm). SimX carried the bit into the warp PC, while release RTL builds drop it implicitly through from_fullPC() PC truncation - a SimX<->RTL divergence reachable from hand-written assembly. Adds a conform test that lands on an intentionally odd JALR target via an overlapped instruction word, so fixed and unfixed builds both decode valid instructions but produce different pass/fail signatures. Runs in CI through the kernel category (simx + rtlsim, both XLENs). Rebase of PR #339 (original targeted the retired sim/simx/execute.cpp). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Review (maintainer)Verified on master @ 1c3403d: bug still live — the JALR path moved to Why CI missed it: only hand-written assembly can produce a misaligned JALR target; nothing in the tree exercised it. Your conform test closes that (CI kernel category runs conform on simx + rtlsim at both XLENs) — no extra CI wiring needed. Code review: clean per Merge mechanics: this branch predates the 3.0 history rewrite (no common ancestor with master, +3600 legacy commits), so it can't be merged or updated in place. The fix and test are landing via #396 with your authorship on the commit. Accepting and closing this PR in favor of #396 — thank you for the fix and the excellent test! |
simx: clear bit 0 of the JALR target address (rebase of #339)
This fixes JALR target address alignment in sim/simx by clearing bit 0 of the computed target, as required by the RISC-V ISA.
It also adds a regression test under tests/regression/jalr.