simx: clear bit 0 of the JALR target address (rebase of #339) - #396
Merged
Conversation
The RISC-V ISA requires JALR to clear bit 0 of the computed target (rs1 + imm). SimX carried the bit into the warp PC, while release RTL builds drop it implicitly through from_fullPC() PC truncation - a SimX<->RTL divergence reachable from hand-written assembly. Adds a conform test that lands on an intentionally odd JALR target via an overlapped instruction word, so fixed and unfixed builds both decode valid instructions but produce different pass/fail signatures. Runs in CI through the kernel category (simx + rtlsim, both XLENs). Rebase of PR #339 (original targeted the retired sim/simx/execute.cpp). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Rebase of #339 by @cassuto onto current master — the original branch predates the 3.0 history rewrite and cannot be updated in place (its fix targeted the retired
sim/simx/execute.cpp; the JALR execute path now lives insim/simx/alu_unit.cpp).What
warp.PC = (rs1 + imm) & ~1(RISC-V ISA requirement).Verification (master @ 1c3403d)
value=0x2468ace0); fixed simx: passes.from_fullPC()PC truncation, so this also restores SimX↔RTL parity.tests/regressionsimx suite: 81/81 pass with the fix applied.Why CI never caught it
Only hand-written assembly can produce a misaligned JALR target (compilers never emit one), and no test exercised it. The conform test added here runs in CI via the kernel category (
kernel.yaml: simx + rtlsim, both XLENs), closing the hole.Commit is authored by @cassuto; closes #339.
🤖 Generated with Claude Code